The implementation of sampling processes on integrated circuits often requires the use of sampling networks or switched capacitor circuits. Switched capacitor circuits allow for discrete time signal processing by applying an input signal to a capacitor when a connected switch is closed. FIG. 1 illustrates a standard capacitive sampling circuit. When switch 20 is closed during the phase φ1, the input signal is applied and a corresponding charge is stored on capacitor 10 that is proportional to the input signal, and this charge is held on capacitor 10 when switch 20 is opened.
While basic switched capacitor circuits such as that illustrated in FIG. 1 are useful in implementing sampling processes, they have a number of drawbacks. Sampling an input signal in a switched capacitor circuit will not only sample the intended input signal, but any accompanying thermal noise. This noise is primarily produced by the switch, such as switch 20 in FIG. 1, in the switched capacitor circuits, and is particularly problematic when used in conjunction with small capacitors. When designing integrated circuits using switched capacitor circuits, consideration must be made for the presence of the sampled noise, especially in integrated circuits that require a high accuracy (such as high-accuracy sample and hold circuits) or high resolution (such as high-resolution data converters). Consideration, in particular, must be made to account for the power produced by the sampled noise. If switch 20 is represented by a simple resistive element having a resistance of RON, the thermal noise power of the sampled noise in a switched capacitor circuit can be expressed by Equation (i):
                              noise_power          =                                    (                              4                ⁢                                                                  ⁢                                  kTR                  ON                                            )                        *                          (                                                1                                                            R                      ON                                        ⁢                    C                                                  *                                  1                                      2                    ⁢                    π                                                  *                                  π                  2                                            )                                      ,                            (        i        )            where k=Boltzmann's constant, T=the absolute temperature in Kelvin, RON=the equivalent resistance of the switching device, and C=the capacitance of the sampling capacitor.
Equation (i) may be further simplified into equation (ii):
                    noise_power        =                              kT            C                    .                                    (        ii        )            
Previous techniques for designing integrated circuits have concentrated on reducing the magnitude of the noise sampled, such as in U.S. Pat. No. 7,298,151 (“the 151 patent”). FIG. 2 illustrates a capacitive sampling circuit with a hold amplifier to reduce sampling noise, as described in the '151 patent. During phase φ1, switches 20 and 22 are closed, connecting capacitor 10 to the input at the bottom plate. When switch 20 is closed, the input signal is applied and stored on capacitor 10. The closing of switch 22 allows for setting a DC potential voltage on the top plate of capacitor 10, allowing for the setting of a charge at node S1, as illustrated in FIG. 2. The charge on capacitor 10 will therefore be proportional to the input voltage less the DC potential at S1. During φ2, switch 21 is closed, and the charge at S1 is frozen. Amplifier 30 is connected to capacitor 10 at node S1, and is used to buffer the sampled input voltage during the hold phase, φ2. During this hold phase, switch 23 is closed, creating a feedback loop for amplifier 30 through capacitor 12. This arrangement, as described in the '151 patent, allows for the sampled noise to effectively have a power that is less than
      kT    C    .While this process allows for the reduction of the noise in the integrated circuit, it does not provide for an actual cancellation of the noise in the circuit. Thus, sampled noise will continue to be present in the system and add to the power output of the integrated circuit.
Other previous configurations have, instead of trying to reduce the noise sampled, attempted to reduce or cancel noise on a capacitor reset to a DC voltage in the designed integrated circuit or used correlated double sampling in imagers that relied on noise being present before a signal is sampled. None of these other previously implemented systems have allowed for an actual cancellation of the noise component from a sampled signal after a sample has already been taken.
Thus there remains a need in the art for a system and a process that cancels the noise sampled on a sampling capacitor after an input signal has already been sampled.